The present invention relates to a manufacturing method of semiconductor devices with interconnection electrodes made of silicide of high melting point metal.
In manufacturing a semiconductor intergrated circuit with multilayered interconnections, an Al interconnection as a first layer can not withstand a high temperature treatment in the manufacturing process of the semiconductor device. The substitution of the Al interconnection by a polysilicon interconnection suffers from high resistivity. In this respect, a proposal in which silicide of high melting point metal such as molybdenum silicide MoSi.sub.2 is used for the interconnection layer, has recently received considerable attention. The proposal, however, has a problem in that when the MoSi.sub.2 layer is used for the interconnection electrode, it is hard to form good ohmic contact of it with a semiconductor region with low impurity concentration, for example, 10.sup.19 /cm.sup.3 or less. The inventor of the present invention proposed an inventive method in which a polysilicon layer is formed on a semiconductor layer and an MoSi.sub.2 layer is further formed on the polysilicon layer. This proposal successfully attained good ohmic contact between the semiconductor region on which the interconnection is formed and the MoSi.sub.2 layer with the polysilicon layer intervening therebetween. This proposal has also some disadvantages. First, the provision of the polysilicon layer needs steps to diffuse n-type impurity material into the polysilicon layer disposed facing an n-type semiconductive region and a step to diffuse p-type impurity material into the polysilicon layer disposed facing the p-type semiconductor region. The diffusing steps make the manufacturing process complicated. Second, in etching the MoSi.sub.2 layer layered on the polysilicon layer to a given reduced dimensional layer, a difference of the etching characteristic between them makes it difficult to accurately form the interconnection. As a result, it is difficult to improve an integration density of the integrated circuit.